# VP of SoC Architecture (AI & Memory Systems) — CyberCoders ## Posting metadata - Canonical source: https://www.linkedin.com/jobs/view/4438773084/ - Provider: LinkedIn - LinkedIn job ID: 4438773084 - Company: CyberCoders - Title: VP of SoC Architecture (AI & Memory Systems) - Primary location: Boston, Massachusetts - Work model: On-site; the role is tied to equipped offices in Boston, MA or Santa Clara, CA, and the Boston listing is classified as on-site - Employment type: Full-time - Compensation: LinkedIn displays a CyberCoders-provided base-pay range of $350,000-$500,000 annually; a mirrored version of the posting lists $300,000-$400,000 base plus bonus and equity - Travel: Not disclosed - Applicants: Numeric applicant count unavailable - Posting age: Approximately 2 days old when checked on September 1, 2026; exact posting timestamp unavailable - Generated: September 1, 2026 at 9:24 AM EDT - Alert email subject: Director, Software Engineer at NetApp - Alert email sender: LinkedIn Job Alerts - Alert email date: September 1, 2026 at 9:18 AM EDT - Alert-matched title: VP of SoC Architecture (AI & Memory Systems) ## Eligibility verification Eligible for optimizer review. The canonical LinkedIn posting identifies the role as Boston, MA and describes well-equipped offices in Boston and Santa Clara plus relocation assistance. Role-specific mirrors classify it as on-site. The Boston location is within Greater Boston, so the role passes the alert's work-model/location gate. The current canonical posting is authoritative over the unrelated email subject. ## Positioning track Executive leader. The VP is expected to remain deeply hands-on in silicon and system architecture while growing a specialized team of SoC architects, system architects, and performance-modeling engineers. ## Fit outcome **FAIL — 6% weighted requirement coverage.** The central mandate is semiconductor architecture, not software, cloud, data, or applied-AI architecture. Keith has strong AI/ML systems leadership, distributed-software architecture, product delivery, and organization-building evidence, but his source materials do not establish the mandatory commercial silicon, SoC, CXL/UALink/ESUN, DDR-memory-subsystem, high-speed data-movement, ASIC, or scale-up-network architecture experience. His Ph.D. is in molecular biology/microbiology and immunology, rather than electrical engineering, computer engineering, or a related hardware field. These are multiple hard gaps, so customization cannot credibly bridge the role. Per the optimizer gate, no resume, cover letter, or LinkedIn connection-request note was generated for this FAIL role. ## Weighted evidence map | Requirement | Weight | Evidence score | Source-supported evidence | Assessment | |---|---:|---:|---|---| | Bachelor's degree in electrical engineering, computer engineering, or a related field; master's or Ph.D. preferred | 2 | 0/3 | Ph.D. and B.Sc. are in molecular biology/microbiology and immunology | Hard gap: degree field is not related to semiconductor or computer hardware engineering | | Track record architecting commercially successful data-movement silicon such as NICs, SmartNICs, IPU/DPU, or CXL devices | 3 | 0/3 | Commercial software, SaaS, cloud, data, and AI products are documented | Hard gap: no commercial silicon-product architecture evidence | | Experience architecting CXL, UALink, or ESUN endpoints | 3 | 0/3 | No source evidence | Hard gap | | Strong understanding of DDR-based memory subsystems | 3 | 0/3 | No source evidence | Hard gap | | Experience building high-speed data-movement SoCs | 3 | 0/3 | No source evidence | Hard gap | | Strong background in high-bandwidth and scale-up hardware networks | 3 | 0/3 | Distributed cloud and data systems are documented, but not hardware interconnect or scale-up-network architecture | Hard gap | | Define SoC/system architecture with ASIC design and software/workload teams | 3 | 0/3 | Extensive software architecture and cross-functional product delivery; no ASIC or SoC architecture | Hard gap | | Grow a team of SoC architects, system architects, and performance-modeling engineers | 2 | 1/3 | Built and led software, AI, cloud, data, and analytics teams, including an 11-engineer AI team and larger technical communities | Transferable leadership only; no specialized silicon-architecture organization evidence | | Familiarity with ML systems and networks | 1 | 2/3 | Deep ML/AI systems background, including AWS AI/ML leadership and production AI platforms | Direct ML-systems evidence, but no ML interconnect/network architecture evidence | Weighted calculation: 4 earned points out of 69 maximum points = 5.8%, rounded to 6%. ## Direct-match strengths - Executive and engineering leadership: built an 11-engineer AI/software organization and led larger technical teams and communities. - AI/ML systems: built production AI platforms and advised more than 200 AWS customers on ML/AI and distributed data systems. - Cross-functional architecture and delivery: repeatedly translated product requirements into software, cloud, data, and AI architectures and production systems. ## Hard gaps and caveats 1. No documented experience architecting commercially successful data-movement silicon, NICs, SmartNICs, IPU/DPU, or CXL devices. 2. No documented CXL, UALink, ESUN, DDR-memory-subsystem, NVLink-internals, ASIC, or high-speed SoC architecture experience. 3. No documented high-bandwidth scale-up hardware-network architecture experience. 4. Degree fields do not match the required electrical/computer engineering or related hardware discipline. 5. Applicant count is unavailable, so the standing 90-applicant ceiling cannot be evaluated; the role was not excluded on that basis. 6. Travel is not disclosed and is treated as a caveat rather than a fit failure. 7. The canonical LinkedIn compensation range differs from a mirrored copy; the canonical $350,000-$500,000 range is used as authoritative. ## Normalized job description ### Position overview CyberCoders is recruiting a VP of Architecture to design a flagship silicon product. The leader will work with software and ASIC design teams to define the SoC and system architecture for a memory-expansion device intended to address memory-capacity bottlenecks in AI infrastructure. ### Key responsibilities - Architect an efficient, high-bandwidth memory-expansion device for scale-up networks. - Grow the team of SoC architects, system architects, and performance-modeling engineers. - Collaborate with the software/workload team to define an efficient architecture and system for solving AI-infrastructure memory-capacity bottlenecks. ### Required qualifications - Bachelor's degree in electrical engineering, computer engineering, or a related field; master's or Ph.D. preferred. - Track record architecting commercially successful data-movement silicon, such as NICs, SmartNICs, IPU/DPU, or CXL devices, ideally supporting memory semantics over the fabric. - Strong background in high-bandwidth and scale-up networks. - Experience architecting CXL, UALink, or ESUN endpoints. - Strong understanding of DDR-based memory subsystems. - Experience building high-speed data-movement SoCs. ### Preferred qualifications - Familiarity with ML systems and networks. - Familiarity with NVLink internals. ### Compensation and benefits - LinkedIn displays a CyberCoders-provided base-pay range of $350,000-$500,000 annually. - A mirrored copy lists $300,000-$400,000 base depending on experience, performance-based bonus, and early-stage equity. - Health, dental, vision, and life insurance. - 401(k) match and daily lunch stipend. - Equipped offices in Santa Clara, CA and Boston, MA. - Relocation assistance; source mirrors conflict on visa sponsorship/authorization language, so that item is not used in the fit decision. ## Artifact metadata - JD capture: Generated for publication. - Resume: Not generated because the role failed the fit gate. - Cover letter: Not generated because the role failed the fit gate. - LinkedIn connection request: Not generated because the role failed the fit gate. - Google Drive: Not used.